0-In Welcomes Mentor Graphics to Its Check-In Partner Program; Collaboration Will Allow Designers to Use 0-In's Assertions With Mentor Graphics' Hardware Verification Products.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Jan. 13, 2003 Today, 0-In Design Automation, the Assertion-Based Verification Company, announced the addition of Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. (Nasdaq:MENT) to the 0-In Check-In Partner Program. 0-In has developed a complete assertion-based verification (ABV ABV Above ABV Alcohol By Volume ABV Abuja, Nigeria (airport code) ABV Assault Breacher Vehicle ABV Accredited Business Valuation specialist ABV Auxiliary Building Ventilation ABV Annual Buy Value ABV Air Bleed Valve ) interoperability strategy based on Verilog RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; and support for Accellera standards. Through the Check-In Program, 0-In and its electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) partners collaborate to provide customers with testbench- and simulator-independent assertions throughout the design and verification cycle -- from the block-level to the system-level. The 0-In Check-In Partner Program will provide customers of 0-In and Mentor Graphics the ability to use 0-In assertions across Mentor Emulation Division's accelerated simulation and emulation products. "Design teams require a comprehensive ABV methodology that supports a common set of assertions across all tools in their verification flows," said Emil Girczyc, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. at 0-In Design Automation. "The 0-In Check-In Partner Program provides design teams with solutions that improve verification productivity, which translates into lower costs and faster time to market. Working with Mentor Graphics, we are expanding the ability of IC designers to assemble best-in-class hardware verification tools for their design flows." The 0-In ABV methodology enables customers to use the same assertions across their entire verification environment, including tools for simulation, formal verification, hardware acceleration and emulation. "Our customers have requested an assertion solution that enables them to keep pace with today's increasing design complexities," explained Eric Selosse, vice president and general manager, Mentor Emulation Division. "Using the Mentor Graphics emulation products with the 0-In ABV suite, design teams can achieve greater design confidence in system level test environments." About Mentor Graphics Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,700 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. 95131-2314. World Wide Web site: www.mentor.com. About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (hardware) Application-Specific Integrated Circuit - (ASIC) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer. (ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. ) and system-on-chip (SoC) designs. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com. Note to Editors: 0-In(R) and CheckerWare(R) are registered trademarks of 0-In Design Automation, Inc. |
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