0-In Hosts Advanced Verification Web Seminar; Industry Experts discuss Leading-Edge Technology.Business Editors/High Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--May 15, 2000 0-In Design Automation, Inc. today issued an invitation for participation in a free, online seminar devoted to functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, for system-on-chip (SOC) designs. The "Advanced Verification Seminar" on May 22, 2000 is a live, interactive event produced by 0-In with support from EDTN EDTN Edition EDTN Electronics Design & Technology Network EDTN The Electronics Design, Technology and News Network and hosted by Education, News and Entertainment Network, the leading provider of Internet-based seminar solutions. Industry Experts Address Verification Problems and Solutions The Web Seminar includes two presentations, the first by Dr. David L. Dill, Associate Professor at Stanford University Stanford University, at Stanford, Calif.; coeducational; chartered 1885, opened 1891 as Leland Stanford Junior Univ. (still the legal name). The original campus was designed by Frederick Law Olmsted. David Starr Jordan was its first president. . Dr. Dill presents "Formal Verification
In the context of hardware and software systems, formal verification : Experiences and Future Prospects" and discusses the challenges of functional verification as well as the strengths and limitations of traditional solutions such as simulation and formal verification. A new approach, semi-formal verification, combines traditional simulation with formal technology in order to deliver the advantages of formal verification without its disadvantages. Dr. Richard C. Ho, Founder of 0-In, presents "Practical Application of Semi-Formal Techniques" and discusses the theoretical background for semi-formal technology as well as its deployment in 0-In's products. Seminar Offers a Unique Chance to Learn The Web Seminar includes many aspects of semi-formal verification technology never before presented in a public forum. "This event represents a unique opportunity for leading-edge design and verification engineers to learn about advanced verification technology in a time- and cost-efficient manner, without leaving their desks," said 0-In CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. Dr. L. Curtis Widdoes. "I am delighted that Dr. Dill and Dr. Ho are able to share their expertise directly with the user community over the Internet." Web Seminar Technology Enables Engineer-to-Engineer Interaction Seminar participants can view the presentations and listen to the presenters live via streaming audio over the Internet. An alternative audio source is available through standard telephones for attendees without streaming audio. During the Q&A period following the presentation, participants can type questions into a Chat window, receiving an immediate response from the presenter. The Web seminar is Monday, May 22, 2000 at 2:00pm PDT/5:00pm EDT EDT abbr. Eastern Daylight Time EDT Eastern Daylight Time EDT n abbr (US) (= Eastern Daylight Time) → hora de verano de Nueva York EDT . Participants must pre-register prior to the seminar. Registration information and technical details for Internet participation are available at http://www.netseminar.com About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company that develops tools that zero-in on functional bugs in ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and IC designs. 0-In was founded in 1996 and is based in San Jose, CA, with a sales office in Boxborough, MA and distribution in Japan through Pacific Design Inc. More information on 0-In is available at http://www.0-in.com. Note to Editors: 0-In(TM) and CheckerWare(TM) are trademarks of 0-In Design Automation, Inc. |
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