Printer Friendly
The Free Library
19,573,962 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

0-In Granted Key Patent in Assertion-Based Verification.


Business Editors/High-Tech Writers

SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.--(BUSINESS WIRE)--Aug. 25, 2003

Today 0-In Design Automation, the Assertion-Based Verification Company, announced that it has been granted U.S. Patent Number 6,609,229, entitled "Method for automatically generating checkers for finding functional defects in a description of a circuit," which covers methods of specifying and generating assertions for use in simulation.

"0-In pioneered assertion-based verification," explained Dr. Curtis Widdoes, 0-In's chairman and chief technical officer. "Very early on, our customers told us that it was critical to make assertions easy to use. With their guidance, we developed a wide range of methods and technologies for design engineers and verification engineers to easily specify and use assertions. The newly granted patent covers those methods and technologies."

0-In is committed to making the power of assertion-based and formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 technologies available to every chip designer and every verification engineer. "We believe that advanced verification technologies are successful only when they are easy enough to use that they can be adopted without the help of specialists," said Dr. Widdoes. "Our goal is to make specification of assertions effortless, so that every member of the development team can put assertions into the design." As part of this effort, 0-In is a strong proponent of standards and interoperability and is an active member of Accellera. The 0-In Assertion-Based Verification suite of tools and CheckerWare(R) verification IP library support Accellera and IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields.  standards.

Products currently being shipped by 0-In incorporate the methods and technologies covered by the newly granted patent.

About 0-In

0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task,  products that help verify multi-million gate application-specific integrated circuit (hardware) Application-Specific Integrated Circuit - (ASIC) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer.  (ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. ) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV ABV Above
ABV Alcohol By Volume
ABV Abuja, Nigeria (airport code)
ABV Assault Breacher Vehicle
ABV Accredited Business Valuation specialist
ABV Auxiliary Building Ventilation
ABV Annual Buy Value
ABV Air Bleed Valve
) solution that provides value throughout the design and verification cycle -- from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for  (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

0-In(R) and CheckerWare(R) are registered trademarks of 0-In Design Automation, Inc.
COPYRIGHT 2003 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2003, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Aug 25, 2003
Words:364
Previous Article:Trade Up Commerce Tees Off With Fortigo; Large Online Seller of Pre-Owned Golf Clubs Realizes Quick Savings on Shipments.
Next Article:Kashya Enters Enterprise Data Protection Market: Breaking Down the Barriers to Long Distance Replication.



Related Articles
IBM PROPERTY SPECIFICATION LANGUAGE SELECTED AS NEW EDA STANDARD.
Axis Systems Announces New Assertion Processing Technology That Accelerates Assertion-Based Verification.
0-In and Axis Systems Develop a Solution to Extend Benefits of Assertions Throughout the Design Flow.
Novas enhances debug technology platform.
0-In Design Automation Introduces Multi-language Assertion Synthesis Tool; Assertion Compiler Enables Industry-Wide Assertion Interoperability.
@HDL Announces Product Family Update with SystemVerilog and PSL Support.
Cadence and 0-In Collaborate to Deliver Superior Assertion-Based Verification.
@HDL at DVCon 2004; Design & Verification Conference March 2-3, 2004.
Renesas Technology Adopts @HDL Assertion-based Functional Verification Solutions.
NEC Picks Real Intent's Verix for Formal Assertion-Based Verification.

Terms of use | Copyright © 2012 Farlex, Inc. | Feedback | For webmasters | Submit articles