0-In Design Automation to Present at Verisity's Worldwide Next-Generation Verification Seminar Series.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Sept. 3, 2003 Seminars will teach engineers how to achieve verification closure in complex chip development projects Today 0-In Design Automation, the Assertion-Based Verification Company, announced that the company will be presenting at Verisity, Ltd.'s (Nasdaq:VRST VRST Virtual Reality Software and Technology VRST Virtual Reality System Testing ) worldwide Autumn seminar series on verification methodology. The Next-Generation Verification Seminars will introduce Verification Process Automation (VPA VPA Valproate VPA Vancouver Port Authority (Canada) VPA Virtual Population Analysis VPA Voluntary Partnership Agreement VPA Voluntary Placement Agreement VPA Volume Purchase Agreement VPA Vermont Principals' Association ) solutions and offer a step-by-step look at what it takes to achieve first-pass silicon success with today's extremely complex chips, systems, hardware and software systems and systems-on-chip. In addition, attendees will get a sneak peek at innovative new verification automation technologies that enable verification closure. The seminars are highly technical, focusing on VPA methodologies and techniques. Verisity will discuss concepts in driving verification closure by using verification metrics and process automation and show how these techniques scale from the module to the chip and the system level. 0-In will discuss structural coverage, a set of unified coverage metrics that link simulation with formal verification
In the context of hardware and software systems, formal verification to provide users with actionable feedback about functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, progress. These metrics support effective use of assertion-based verification, reduce total verification effort, and allow for earlier tape out with greater confidence. At the seminars, attendees will learn: -- Strategies that deliver results, beginning with verification plan creation -- Total coverage as the metric for verification closure -- Use of static, simulation, and formal structural coverage for best results -- How an assertion methodology fits into an overall testbench strategy -- Automation of the verification process -- Verification reuse strategies that improve efficiency and deliver results. Seminar Schedule and Registration The Next-Generation Verification seminar series will be offered worldwide; 0-In will participate in all the seminars in North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. , Japan and Korea as follows: September 15: Los Angeles Los Angeles (lôs ăn`jələs, lŏs, ăn`jəlēz'), city (1990 pop. 3,485,398), seat of Los Angeles co., S Calif.; inc. 1850. , CA September 16: Irvine, CA September 17: San Diego, CA September 23: Santa Clara, CA October 7: Ottawa, ON October 9: Waltham, MA October 14: Denver (Broomfield), CO October 21: Dallas, TX October 23: Austin, TX October 31: Kyoto, Japan November 5: Tokyo, Japan November 7: Seoul, Korea Attendance at the seminars is free. Registration information and more details on the seminar contents are available at http://www.verisity.com/home/seminar2003/index.html or by sending an email to seminars@verisity.com or seminars@0-In.com. About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (hardware) Application-Specific Integrated Circuit - (ASIC) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer. (ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. ) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV ABV Above ABV Alcohol By Volume ABV Abuja, Nigeria (airport code) ABV Assault Breacher Vehicle ABV Accredited Business Valuation specialist ABV Auxiliary Building Ventilation ABV Annual Buy Value ABV Air Bleed Valve ) solution that provides value throughout the design and verification cycle -- from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com. Note to Editors: 0-In(R) and CheckerWare(R) are registered trademarks of 0-In Design Automation, Inc. |
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