0-In Announces National Semiconductor Signs Corporate License for White-Box Verification Products; 0-In tools Deployed Throughout National's Design Centers.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Oct. 30, 2001

Today 0-In Design Automation, Inc., the leader in white-box verification technology, announced that National Semiconductor Corporation has purchased a multi-year, worldwide corporate license for the 0-In suite of white-box verification tools. This agreement enables all development teams at National to use 0-In Check, 0-In Search, and the 0-In CheckerWare library for verification of system-on-chip (SOC) designs.

0-In Methodology Validated on Information Appliance Chip Design

"National has used an internally-developed assertion methodology for several years. Our corporate commitment to 0-In is the direct result of the additional benefits their tools and methodology demonstrated on a recent complex chip design," said Ron Wawrzynek, Vice President, Engineering, Information Appliance (IA) Group at National Semiconductor." The pilot project was an integrated companion chip to the Geode(TM) processor with sophisticated I/O capabilities. 0-In's dynamic-formal verification technology is an effective product for validating complex interfaces and the resulting interactions. The use of 0-In Check and 0-In Search enabled us to find specification and design corner-case errors that may have been missed using only simulation-based verification."

0-In Assertion-Based Verification Supports Platform-Based Design and Reuse

"As part of the pilot project, 0-In created two custom Checkerware monitors for proprietary system buses in the IA chip family," said Gordon Mortensen, Director of Information Appliance Chipset Design and Verification at National Semiconductor in Santa Clara. "These monitors served to clarify several specification ambiguities by providing an accurate representation of the bus specifications. Using these monitors in simulation and dynamic-formal verification not only found interface bugs, they also measured how effectively our test suite covered the bus protocol. 0-In Search identified corner case bugs that probably would not have been found prior to tape out. These monitors will soon be used in the verification of future designs based on this architecture. The design and verification team at National Semiconductor working on the pilot project received excellent training, and technical support from 0-In."

0-In Tools Available to National Design Groups Worldwide

"We are very pleased that National Semiconductor has significantly expanded its commitment to 0-In and has become one of our largest corporate customers," said 0-In CEO Dr. L. Curtis Widdoes. "National's standardization on 0-In products for assertion-based simulation and dynamic-formal verification ratifies 0-In's position as the leader in white-box verification. National design teams in multiple locations have already had experience with 0-In tools and are adopting them more widely for ongoing and future projects."

About 0-In

0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA) company providing functional verification products that help verify multi-million gate ASIC and SOC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Scituate, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Avaz Networks, Compaq, Fujitsu, HP, Hitachi, Hughes, Lucent, National Semiconductor, Nortel, Sun, Tensilica and others. More information on 0-In is available at http://www.0-in.com

Note to Editors: 0-In(TM) and CheckerWare(TM) are trademarks of 0-In Design Automation, Inc. Geode(TM) is a trademark of National Semiconductor Corporation.