0-In Announces CheckerWare Interoperability Plans; Multi-Faceted Program Eases Adoption of Assertion-Based Verification.Business Editors/High-Tech Writers SAN JOSE--(BUSINESS WIRE)--Jan. 28, 2002 Today 0-In Design Automation, Inc., The Assertion-Based Verification Company, announced its assertion interoperability The capability of two or more hardware devices or two or more software routines to work harmoniously together. For example, in an Ethernet network, display adapters, hubs, switches and routers from different vendors must conform to the Ethernet standard and interoperate with each other. plans and programs. These efforts aim to speed the adoption of assertion-based verification through standardization standardization In industry, the development and application of standards that make it possible to manufacture a large volume of interchangeable parts. Standardization may focus on engineering standards, such as properties of materials, fits and tolerances, and drafting efforts and open access to 0-In CheckerWare. Assertion-Based Verification is Necessary to Validate Today's Complex ICs Design assertions document important design assumptions and constraints CONSTRAINTS - A language for solving constraints using value inference. ["CONSTRAINTS: A Language for Expressing Almost-Hierarchical Descriptions", G.J. Sussman et al, Artif Intell 14(1):1-39 (Aug 1980)]. for correct functionality of a designer's RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; code. Assertion-based verification tools respect these assertions to increase verification effectiveness; they ensure that assertions are not violated vi·o·late tr.v. vi·o·lat·ed, vi·o·lat·ing, vi·o·lates 1. To break or disregard (a law or promise, for example). 2. To assault (a person) sexually. 3. during simulation and they apply formal methods to further increase confidence that these assertions cannot be violated. The design industry has recognized the importance of assertions and assertion interoperability. Through the Accellera standards group, many proposals are being discussed from comprehensive formal languages to simple Verilog assertion libraries. There is significant work to be done to arrive at a final standard. Once the standard is established, 0-In will move to incorporate support in its tools, but today, the industry has numerous, incompatible, proprietary assertion formats which are available from multiple sources. This lack of interoperability is limiting the rate of adoption of assertion-based verification and reducing the effectiveness of design verification. To enable design groups to start adopting assertion-based verification now, 0-In has embarked on an assertion interoperability program that provides open access to its assertions and tools to qualified customers and partners. Interoperability is achieved through a simple exchange format consisting of synthesizable RTL Verilog and a primitive assert construct which enables customers and tool vendors to recognize 0-In CheckerWare and CheckerWare Monitors with minimal tool modification, and thus, reduce the time required to introduce support. 0-In Supports Multiple Efforts to Achieve Interoperability 0-In is engaged in multiple interoperability and CheckerWare access programs to achieve interoperability in the short term and to continuously improve it over time. Accellera Assertion Standardization -- in progress 0-In is a member of Accellera and participates actively in efforts to develop industry-standard assertions for verification. Once relevant standards are agreed upon Adj. 1. agreed upon - constituted or contracted by stipulation or agreement; "stipulatory obligations" stipulatory noncontroversial, uncontroversial - not likely to arouse controversy , 0-In is committed to incorporate these standards into its products and flows. Assertion Exchange Format -- pragmatic interoperability that works now Designers using assertion-based verification need a way to drive multiple verification tools today. 0-In has developed an easy to implement and adopt assertion interoperability strategy based on RTL Verilog and a simple assert construct. This approach is compatible with Accellera's interoperatility goals and is available today for 0-In assertions via the Check-In Partner Program. Free Access to Learn Assertion-Based Verification Techniques 0-In will provide access to the Check-Lite software, assertion library, and training material free of charge to enable companies to explore and develop assertion-based verification techniques. Open Extensibility 0-In provides tools and support to enable customers to create proprietary assertions. Via its interoperability programs, these assertions can be linked to customer internal, 0-In, and third party EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools. Interoperability is Crucial for Broad Adoption of Assertion-Based Verification "0-In was the first commercial EDA vendor to recognize that assertions are part of the design, not part of the design tools or test bench," said Dr. L. Curtis Widdoes, Founder and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of 0-In. "Our customers need assertion standards and interoperability to enable designer-specified assertions to drive all tools in their verification flow. 0-In fully supports assertion interoperability, and the plans we unveil today support both standardization and open access to our proprietary assertions: the 0-In CheckerWare library and CheckerWare Monitors." "White-box assertions form an important part of the design documentation and verification flow," said Dave Burgoon, Senior Productivity Engineer, Hewlett-Packard Technical Computing computing - computer Center. "Pragmatic approaches, such as those planned by 0-In, let designers specify assertions once and leverage them to drive multiple tools in their verification flow." "As an IP vendor, including assertions with our IP release helps customer verify that they have properly integrated our IP into their circuitry," said Kaushik Sheth, Chief Engineer, Tensilica. "Interoperable The ability for one system to communicate or work with another. See interoperability. assertions such as those from 0-In are key as they enable the assertions we include with our IP to work with the myriad of tools that our customers have in their verification flows." About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA) company providing functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, products that help verify multi-million gate ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and SOC designs. 0-In was founded in 1996 and is based in San Jose San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , CA, with sales offices in Scituate, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. , Avaz Networks, Compaq, Fujitsu, HP, Hitachi, Hughes, Lucent, National Semiconductor, Nortel, Sun, Tensilica, Teradiant Networks and others. More information on 0-In is available at http://www.0-in.com 0-In(R), CheckerWare(TM), and dynamic formal(TM) are trademarks of 0-In Design Automation, Inc. |
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