0-IN-DESIGN UNVEILS HYPERTRANSPORT PROTOCOL MONITOR.0-In Design Automation, Inc., San Jose, Calif., a leader in white-box verification technology, has introduced a CheckerWare monitor for the HyperTransport(TM) I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output Link Protocol standard. HyperTransport technology, developed by AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. , provides low latency, low pin-count, high-speed transaction capabilities between chips inside computers and communication devices. The 0-In development team utilized the AMD simulation environment to verify and ensure that the 0-In HyperTransport monitor is compliant with the latest version of the HyperTransport Specification. 0-In Monitor Validated with AMD HyperTransport Design "The availability of 0-In's HyperTransport CheckerWare monitor helps promote and drive momentum towards the widespread adoption of this new industry standard," said Gabriele Sartori, director of Technology Evangelism for AMD's Computation Products Group. "A robust protocol monitor supporting both simulation and formal-based verification will assist many companies designing HyperTransport interfaces into their chips." Co-operation with AMD Key for Robust Monitor Development "0-In CheckerWare monitors in conjunction with 0-In Search both represent the only practical way to apply formal verification technology to validate a complex protocol such as HyperTransport," reported 0-In CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. Dr. L. Curtis Widdoes. "To ensure the accuracy of new CheckerWare monitors, we work with a development partner who has already implemented the standard in a chip design. The result is a robust protocol monitor that is essentially an executable specification for the standard, usually more precise and accurate than the written document itself. In the case of HyperTransport, we were very fortunate to work directly with AMD's simulation environment, the very same used to verify HyperTransport products under development at AMD, to validate our own monitor. Our access to HyperTransport product designs within AMD enabled 0-In to achieve much more thorough verification of our monitor." About HyperTransport(TM) Technology HyperTransport technology is a high-speed, high-performance, point-to-point link for integrated circuits. HyperTransport technology provides a universal connection that is designed to reduce the number of buses within the system, provide a high-performance link for embedded applications, and enable highly scalable multiprocessing systems. It was developed to enable the chips inside of PCs, networking and communications devices to communicate with each other up to 48 times faster than with some existing bus technologies. About the 0-In HyperTransport Monitor 0-In's HyperTransport Monitor is based on the HyperTransport I/O Link Protocol Specification. It supports many modes and features of the HyperTransport Protocol including End, Node, and Bridge implementations, all CAD widths, error handling and low-level link initialization in·i·tial·ize tr.v. in·i·tial·ized, in·i·tial·iz·ing, in·i·tial·iz·es Computer Science 1. To set (a starting value of a variable). 2. To prepare (a computer or a printer) for use; boot. 3. . For a more complete description, see the overview datasheet at http://www.0-in.com/products/monitors/hypertransport.html. "As a member of the HyperTransport Technology Consortium, we are committed to update the 0-In HyperTransport Monitor to reflect new releases of the specification," said Dr. Widdoes. "By simply updating to a new version of the 0-In monitor, customers automatically update their verification suite to the new version of the HyperTransport specification." About the 0-In CheckerWare Monitor Family 0-In CheckerWare monitors are Verilog protocol monitors that capture and check the complete set of cycle-by-cycle protocol rules for complex standard buses and interfaces. By using these monitors at the block-level and chip-level interfaces in designs, customers can catch interface violations as soon as they occur. CheckerWare monitors accelerate the rate of debugging of sub-modules and blocks as they are integrated into system-on-chip (SOC) designs. CheckerWare Monitors support both simulation and dynamic formal verification. With CheckerWare monitors and the 0-In(R) white-box verification tool suite, design teams can leverage their existing simulation environment and exercise corner cases that are virtually impossible to explore with traditional bus functional models and simulation. CheckerWare Monitors are portable, they work with any testbench, and they do not rely on proprietary languages. The CheckerWare product line now includes monitors for HyperTransport, CSIX, PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). , PCI-X (PCI eXtended) An enhanced PCI bus technology originally developed by IBM, HP and Compaq that is backward compatible with existing PCI cards. PCI and 32-bit PCI-X slots are physically the same, and PCI cards can plug into PCI-X slots. , Low Pin Count (LPC (language) LPC - A variant of C designed ca 1988 to program LP MUDs. ), UTOPIA Levels 1-4, POS-PHY Levels 2-4, SPI-4, and the AMBA AMBA Area Metropolitana de Buenos Aires (Spanish) AMBA Advanced Microcontroller Bus Architecture AMBA American Mold Builders Association AMBA American Mustang and Burro Association AMBA Association of Master of Business Administration buses for the ARM microprocessor. Monitors are also available for several memory interfaces, including SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. , Double Data Rate (DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM. DDR - Double Data Rate Random Access Memory and DDR2) SDRAM and Quad Data Rate Quad data rate (or quad pumping) is a communication signalling technique wherein data is transmitted at both the rising and falling edges of the clock signal, much the same way DDR technology works, but with two clock signals 90° out of phase from each other, effectively (QDR QDR Quadrennial Defense Review (US DoD) QDR Quad Data Rate (Memory Technology) QDR Quality Deficiency Report QDR Quality, Durability and Reliability (Toyota Motor Company) ) SRAM See static RAM. SRAM - static random-access memory . About 0-In 0-In Design Automation, Inc. (pronounced "zero-in") is a privately held electronic design automation (EDA) company providing functional verification products that help verify multi-million gate ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and SOC designs. 0-In was founded in 1996 and is based in San Jose, CA, with sales offices in Scituate, MA and Austin, TX plus distribution in Japan through Pacific Design Inc. Leading-edge companies that have adopted 0-In tools and methodologies include AMD, Avaz Networks, Compaq, Fujitsu, HP, Hitachi, Hughes, Lucent, National Semiconductor, Nortel, Sun, Tensilica, Teradiant Networks and others. For more information, visit http://www.0-in.com or call 408/487-3603. |
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