[0] Sequence Leads With NanoCool Flow; Blueprint for Low-Power/Low-Voltage 100 nm SoC Design.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 25, 2002

Sequence Design Inc., the SoC Design Closure Company, today announced NanoCool, the company's initiative for low-power/low-voltage design. The purpose of this initiative is to develop a flow that addresses the unique needs of SoC design at 100 nanometers and below. Companies in the optical networking, wireless, data processing, mobile computing and consumer electronics markets will benefit greatly from this solution.

The initiative will produce a low power/low voltage design flow capable of identifying potential problems caused by power consumption and power distribution, fixing them, and validating the fixes before tape out. Sequence believes that unless design automation companies develop a focus on power, the design gap will widen beyond where it is now as companies move to feature sizes of 100 and 90 nanometers. At these small geometries the margin for error is so narrow that you can no longer produce high-yield designs without considering power from top to bottom. Power is important at every point in the flow.

Sequence's leadership position in power, noise and timing optimization, and high accuracy extraction form the foundation for this initiative. On top of this foundation Sequence is building the next generation of EDA capabilities which are specifically targeted at low voltage, nanometer problems such as minimization of both dynamic and leakage currents, noise margin analysis and optimization, and reliability verification. Low-voltage scaling has always been considered an anathema in terms of analog circuit performance. But even digital experts are recognizing that increases in leakage currents and decreases in noise margins are resulting in noisy power hogs in portable systems. The overall focus of Sequence's efforts will be the concurrent analysis and optimization of power, timing, and noise. The initiative will include both high level prediction and optimization coupled with successive refinements and optimizations at lower levels to help designers achieve design closure.

"The critical success factor in design has moved from decreasing die size to power management. 100 nanometers provides a fundamental inflection point for design," said Vic Kulkarni, chief operating officer, Sequence Design. "We have developed the blueprint for our NanoCool flow by listening closely to what our customers have told us is critical for this level of design. As a result NanoCool will offer designers the ability to reduce leakage and dynamic power, perform noise analysis, repair noise issues, and optimize for timing in the face of challenges such as a noisy environment with huge currents flowing through power rails. NanoCool will tackle all of these challenges by providing advanced power optimization capabilities, including dual-threshold optimization, and noise analysis and mitigation tools, such as our new version of ShowTime for dynamic power rail analysis."

The initiative will involve the participation of IP providers, other EDA software providers, and end users in order to complete the entire solution chain. Silicon Metrics will work with Sequence to add noise and SI modeling capabilities to their characterization and modeling software. Previously, Silicon Metrics and Sequence partnered to develop power modeling support. Virtual Silicon will produce low leakage IP that will be qualified within the Sequence power optimization flow. These new capabilities, when incorporated in Sequence's NanoCool flow, will enable users to achieve new levels of analysis and optimization for power and noise in low voltage, UDSM designs. The initiative will be completely open and participation in the initiative will be encouraged through the use of industry standard interfaces and formats.

Sequence's partners have commended the company for its leadership in developing a solution for100 nanometer low-power/low-voltage design. "The combination of power management with noise analysis and repair is critical for low-power/low-voltage nanometer design. Our leading-edge cross-talk and glitch characterization technology is a key component of the solution," said Callan Carpenter, CEO, Silicon Metrics. "We wholeheartedly support the NanoCool initiative."

"In order to effectively use low-power, low-voltage standard cells, memories, I/Os and high speed interfaces at 0.10 micron, there are silicon-critical issues in modeling and managing static and dynamic power consumption that have yet to be solved," said Ken Brock, director of corporate marketing at Virtual Silicon. "Sequence's leadership in addressing these issues will enable designers to efficiently use our pre-characterized components in their million-gate designs."

The Methodology

The methodology starts with an exploration of the design space in order to create circuit architecture optimized for power. It will include analysis-based optimization of the effects of power on temperature and timing, as well as determining the impact of thermal gradients on power and timing. These effects produce positive feedback on one another that must be anticipated. The methodology will also incorporate not only a timing sign-off, but also a power sign-off, a task not commonly performed today.

"Sequence has the vision for addressing power and leakage management. Concurrent optimization is the only way to achieve a single-pass route to efficient silicon implementation from a microarchitecture," said Dr. Jan Rabaey of the University of California at Berkeley. "A platform architecture must be developed that combines static and dynamic techniques in order to address voltage, frequency, threshold issues and thereby minimize power dissipation while meeting performance constraints."

The Design Flow

During the initial stages of the process, while RTL is being developed, the designer will be able to explore design alternatives and perform power tradeoffs. For example, the designer will be able to partition their design into voltage domains supplied by multiple voltage sources. This partitioning will enable substantial reductions in dynamic power consumption. Such exploration will permit initial evaluation of the design's power, area, timing and thermal requirements.

"A comprehensive methodology is needed for nanometer low-power/low-voltage design," said Scott Van Sooy, director of Broadcom's broadband processor business unit. "Lowering voltage has the biggest impact on reducing power, however the effect this has on performance, noise margins, and power distribution must be managed. A multi-level, concurrent optimization capability should be employed to effectively address these tradeoffs."

The key components of the NanoCool flow are:

-- Architectural Exploration for Power Reduction

-- IP Power Modeling

-- Vectorless Power Analysis

-- Power Grid Design, Analysis and Verification

-- Dynamic Power Reduction

-- Leakage Power Reduction

-- Reliability Analysis

-- Noise Margin Analysis

-- Advanced Delay Calculation & STA, including noise & coupling (in ShowTime)

About Sequence

Sequence Design, Inc., the SoC Design Closure CompanySM, enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to tapeout. Sequence's physical design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer design.

Sequence has worldwide development and field service operations. The company was formed through the merger of Sente, Inc., Sapphire Design Automation, Inc. and Frequency Technology. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM)and Mentor Graphics' Open Door(TM)partnership programs.

Note to Editors: Sequence Design, NanoCool, and ShowTime are trademarks of Sequence Design. Broadcom(R) is a trademark of Broadcom Corporation and/or its affiliates in the United States and certain other countries. All other trademarks are the property of their respective owners