[0] PMC-Sierra Unveils Industry's Highest Performance MIPS Multiprocessor Architecture.

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SAN JOSE, Calif.--(BUSINESS WIRE)--June 11, 2001

RM9000x2(TM) Integrated Multiprocessor Features Dual GigaHertz CPUs to

Address the Performance and Low Power Requirements of the

Communications Market

Today at the Embedded Processor Forum, PMC-Sierra (Nasdaq:PMCS) introduced the architecture for the RM9000x2(TM) integrated multiprocessor, the company's next generation high performance MIPS processor designed for the communications market.

The RM9000x2 is a scalable multiprocessing architecture that solves the industry-wide problem of slow data transfers between processors in cache coherent systems and offers greater throughput efficiencies over single CPU products. Anchored by dual CPU cores running at 1 GHz, the RM9000x2 achieves maximum performance while drawing only five watts of power. Using 0.13 micron high performance process, the GigaHertz CPU speed and low power is achieved. The twin CPUs connect to high speed memory and I/O interfaces through a multiport, shared memory fabric. High speed I/O connectivity, which includes a very high performance 500 MHz HyperTransport(TM) bus interface, positions the RM9000x2 to target key applications such as core routers, edge routers, remote access products and enterprise servers.

"Networking is inherently a parallel operation and PMC-Sierra has adapted its microprocessor design to the requirements of high speed processing within networking equipment," stated Tom Riordan, vice president and general manager of the MIPS Processor Division at PMC-Sierra. "The RM9000x2 architecture is the foundation for future products that will provide greater processing power through additional CPU cores and higher performance I/O interconnect designed for networking equipment."

"PMC-Sierra's MIPS design team has a long standing history of delivering leading-edge processor architectures," said Markus Levy, senior analyst at MicroDesign Resources. "At 1 GHz, the RM9000x2 dual processor establishes a new standard for high performance networking, eliminating the single CPU architecture with a unique and highly integrated system solution poised to solve the multiprocessing bottleneck."

RM9000 CPU Subsystem Is Optimized For Performance

At the heart of the CPU subsystem are two RM9000 64-bit MIPS CPU cores that are compatible with the MIPS(TM)-64 instruction set architecture. Each core has a sophisticated cache architecture which includes high performance level 1 instruction and data caches, as well as 256 Kbit of level 2 cache, providing a total of 512 Kbit of level 2 cache for both cores. The large level 2 cache is ideal for storing networking related data structures such as routing look-up tables. The level 1 cache accesses are at the core frequency and with the RM9000x2, access to the tightly coupled level 2 cache is only five CPU cycles. The ability to access the cache so quickly allows the CPUs very fast access to instructions and data and gives the RM9000x2 best-in-class performance for a GHz multiprocessor. Fast Packet Cache(TM) mode allows bypassing of level 2 cache on a per page basis which greatly improves packet processing performance.

The CPU cores have the flexibility to function either with or without hardware cache coherency and allow the RM9000x2 to address a variety of applications. In a non-coherent configuration, the CPUs can be separated into control and data plane processors that provide the foundation for an edge router. A cache coherent CPU subsystem extends the processing power of a single CPU and delivers the high performance needed by a core router exception processor or an enterprise server.

The dual RM9000s are connected to each other by a CPU switch and enable cache transfers between the processors at the CPU core frequency. This architecture solves an industry-wide problem of slow data transfers between processors in cache coherent systems by delivering 51.2 Gbit/s of inter-CPU bandwidth. To accelerate the multiprocessing capabilities, a five-state cache coherency protocol is used. The five state Modified/Owned (Modified-Shared)/Exclusive/ Shared/Invalid (MOESI) protocol extends the functionality of the standard Modified/Exclusive/ Shared/Invalid (MESI) protocol to permit one processor to share modified data from the other processor's cache. A packet processing application could benefit from this by using one CPU to do the initial processing and the second CPU to finish processing while keeping the packet within cache. Sharing modified cache lines minimize access to the main memory, further increasing the RM9000x2 processor performance. Full hardware I/O coherency is supported over the HyperTransport and SysAD interfaces and enables I/O devices access to coherent memory without software intervention.

Shared Memory Fabric Switches the Data

The shared memory fabric is a high bandwidth data switch that improves overall performance by supporting concurrent data transfers on multiple ports. The shared memory fabric, for example, will allow a CPU access over SysAD at the same time that a HyperTransport peripheral is accessing the main memory. Switching data concurrently eliminates the costly bottlenecks that occur in bus-based architectures and provides the fastest possible connectivity between the CPUs, SDRAM and I/O devices.

High Performance Busses Increase System Bandwidth

The integrated high speed bus interfaces, which includes DDR SDRAM, HyperTransport, SysAD and a local bus, provide low latency accesses into the main memory and high bandwidth to the I/O devices. The 200 MHz DDR memory controller offers 25.6 Gbit/s of memory bandwidth and has the flexibility to support both DDR SDRAM and the lower latency DDR FCRAM. Up to two Gigabytes of main memory can be addressed using 512 Mbit/s devices and the memory bus includes ECC protection. The HyperTransport I/O bus is new to PMC-Sierra's architecture and is based on an AMD standard. It is a 500 MHz DDR bus that delivers 16 Gbit/s of raw bus bandwidth for maximum performance. The

HyperTransport interface provides easy connection to a wide range of high speed networking peripherals. The SysAD bus is the same processor bus that is used on the RM7000(TM) and RM5200(TM) product families. The addition of a SysAD bus on the RM9000x2 enables connectivity to all SysAD-based peripheral devices and delivers a seamless upgrade path for existing RM7000 designs. The local bus provides a boot bus and connectivity to slower speed devices.

Additional RM9000x2 Features

The RM9000x2 provides very fast on-chip memory with 8 KB of integrated scratch RAM that is ideal for holding networking-related data structures such as descriptors and header information. A flexible, prioritized interrupt controller supports 256 HyperTransport interrupts, 10 external interrupts and interprocessor interrupts to support multiprocessing. A four-channel DMA controller provides high speed "any port-to-any port" data transfers between HyperTransport, SysAD, the main memory and integrated scratch RAM. The RM9000x2 supports EJTAG debug with debug modules integrated into each CPU. The EJTAG debug strategy ensures smooth debugging of both the hardware and software.

Availability

PMC-Sierra will begin sampling the RM9000x2 in Q4 of 2001. Evaluation boards will be available in Q1 of 2002.

About PMC-Sierra

PMC-Sierra is accelerating the broadband revolution. PMC-Sierra's extensive family of broadband communication semiconductors enables the equipment that makes up the backbone of the Internet. PMC-Sierra offers worldwide technical and sales support including a network of offices throughout North America, Europe and Asia. PMC-Sierra is publicly traded on the Nasdaq Stock Market under the symbol "PMCS". The company is included in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. The Nasdaq-100 Index is the benchmark for the Nasdaq-100 Index Tracking Stock (Amex:QQQ).

PMC-Sierra develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1, T3/E3, Voice-over-Packet, wireless infrastructure, MIPS microprocessor, and Gigabit Ethernet solutions for wide area network (WAN), and Internet networking equipment. The company's quality system is registered with the Quality Management Institute to the ISO 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to define and develop interoperable, standard-compliant solutions for high speed networking applications. For more information about PMC-Sierra, visit http://www.pmc-sierra.com.

Attachments:
Figure 1:  RM9000x2 Block Diagram
Figure 2:  RM9000x2 Applications
Technical Glossary

Technical Glossary
------------------
AMD              Advanced Micro Devices, Inc.
ATM              Asynchronous Transfer Mode
CPU              Central Processing Unit
DDR              Dual Data Rate
DMA              Direct Memory Access
ECC              Error Correcting Code
EJTAG            Enhanced Joint Test Action Group.  The adoption of a
                  single, industry-standard debugging interface for
                  the MIPS architecture
FCRAM            Fast Cycle Random Access Memory
Gbit/s           Billion bits per second
GHz              GigaHertz
I/O              Input/Output
IP               Internet Protocol
KB               KiloByte
Kbit             A thousand bits
MESI             Modified/Exclusive/Shared/Invalid
MHz              MegaHertz
MIPS             Millions of Instructions Per Second
MOESI            Modified/Owned (Modified-Shared)/Exclusive/Shared/
                  Invalid
RAM              Random Access Memory
RM9000x2(TM)     PMC-Sierra's RISCMark 9000x2(TM) MultiProcessor
                  Architecture
SATURN(R)        PMC-Sierra works with over 30 member companies to
                  define and develop interoperable, standard-compliant
                  solutions for high speed networking applications
SDH              Synchronous Digital Hierarchy
SDRAM            Synchronous Dynamic Random Access Memory
SONET            Synchronous Optical Network
SysAD            Multiplexed Address/Data System Bus
T1               North American standard for 1.544 Mbit/s transmission
T3               North American standard for a TDM
                  digital channel carrier that operates at
                  44.736 Mbit/s. It can multiplex 28 DS-1 signals and
                  is synonymous with DS-3
WAN              Wide Area Network

(c) Copyright PMC-Sierra, Inc. 2001. All rights reserved. SATURN(R)is a registered trademark of PMC-Sierra, Inc. RM9000x2(TM)Integrated Processor, RM7000(TM), RM5200(TM)and PMC-Sierra(TM)are trademarks of PMC-Sierra, Inc. HyperTransport(TM)is a trademark of AMD, Inc.

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