@HDL Attacks Complex SOC Verification With Adaptive Functional Technology.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--May 21, 2001

Richard Curtin Joins @HDL as COO, Reunites with Former Frontline

Verilog Engineering Team to Accelerate the Functional

Verification Cycle

Three software development engineers, formerly founders of Verilog cycle-based simulation pioneer Frontline Design Automation, and that company's former vice president of sales and marketing today launched @HDL, Inc. @HDL is an electronic design automation (EDA) company focused on providing Adaptive Functional Verification (AFV) technology that accelerates system-on-chip (SOC) verification and debugging, and completes the "Intelligent RTL Testbench" methodology.

"Today's SOC development schedule assigns upwards of 60-70 percent of the time to functional verification. Our mission is to bring an adaptive methodology to SOC verification that leverages both formal model checking and intelligent-random simulation technologies to allow correction of tough logic errors early in the RTL coding process," said Badru Agarwala, president, CEO and co-founder of @HDL. "Verification engineers don't have to be Ph.D.s to use our automatic formal model checking. When combined with smart Verilog simulation and SOC/silicon IP integration-level analysis and debugging, engineers can eliminate the most difficult problems in their RTL code."

@HDL was founded in 1999 by four verification experts: Badruddin Agarwala, president and CEO, Vivek Bhat, vice president of engineering, HDL technology, Tarak Parikh, vice president of products -- all former founders of Frontline Design Automation -- and Yusuf Attarwala, vice president of engineering, user interfaces, who previously worked at Avant!. Together, the @HDL management team has more than 100 years of experience in the EDA industry, Verilog design, and verification tool development.

Like Frontline, the company is backed by EDA veteran and "father" of Verilog, Dr. Prabhu Goel, and includes funding support from industry luminary S. Atiq Raza, founder of Raza Foundries, and I.A.I. LLC Venture. The company received $2.5 million in first round funding in early 2000.

Richard Curtin joins @HDL as COO. Since the successful acquisition of Frontline by Avant! in 1997, he has held senior management positions in three EDA startups. Most recently, Curtin was senior vice president sales and marketing at Xpedion Design Systems, a supplier of RF and microwave verification tools. He has more than 16 years of business development, sales, marketing and channel management experience in the EDA market, working during the start-up stages at Viewlogic Systems, Frontline Design Automation, Interra, and Simpod. Curtin holds a Masters of Business Administration from Pepperdine, a Masters of Science, Electrical Engineering, from Cornell, and a Bachelor of Science, Computer Engineering, from Boston University.

"Functional verification is still the most critical issue and time consuming part of chip design, and therefore, a tremendous EDA market opportunity," said Curtin. "We're bridging formal and simulation-based approaches to deliver a complete tool suite for Adaptive Functional Verification of IP blocks and SOCs. We recognize that engineers will not abandon their simulators or rely solely on formal point tools to handle their toughest verification tasks. What they require is a balanced approach that takes advantage of both techniques applied at the appropriate times to validate RTL code at the IP block and system levels. @HDL has the vision and world-class technical expertise to take the final step in enabling the 'Intelligent RTL Testbench' methodology to deliver more effective SOC-level verification solutions."

About the "Intelligent RTL Testbench" Methodology

As described by Dataquest's EDA industry analyst Gary Smith, the "Intelligent RTL Testbench" is basically a methodology that fully automates the functional verification tool flow. Functional verification for SOCs consists of a number of steps from debugging a few lines or modules of RTL code to individual IP blocks to the collection of blocks that integrate the entire SOC.

SOC verification engineers use a variety of tools including traditional gate and RTL simulators, formal equivalency checking tools for comparing synthesized, gate-level descriptions back to the original RTL descriptions, formal model, property, and design rule checking tools, and semi-formal analysis tools. Unification of these tools and capabilities into a comprehensive, RTL testbench methodology that spans IP block and SOC creation, simulation, and synthesis is the challenge that @HDL is addressing.

DAC Demonstrations

@HDL will exhibit at the 38th Design Automation Conference (DAC) to be held in Las Vegas, Nevada from June 18-22, 2001. The company will demonstrate its products in DAC booth No. 841. @HDL's DAC exhibitor presentation will be at 5:45 p.m. in room N119-N120 on Monday, June 18th. For more information, visit www.athdl.com.